Every cycle, the same dynamic plays out. Institutional investors get caught over-exposed at the peak because sell-side consensus is still upgrade-cycling on bookings momentum. They get caught underweight at the trough because the inventory write-down headlines are still hitting the tape when the forward indicators have already turned. The reason this keeps happening isn't that investors are unsophisticated. It's that they're looking at lagging data and calling it a signal.
The five indicators I'm going to walk through aren't secret. Every operator in this industry knows them. What most investors miss is the sequencing…which indicators lead, which lag, how they interact with each other, and critically, what happens when they diverge. That divergence is where the alpha lives.
Let me be direct about the framework's design principle before we get into the indicators themselves: this is a composite system, not a checklist. Any single indicator read in isolation will mislead you. The book-to-bill ratio at 1.2 looks constructive until you see lead times compressing at the same time, that combination means customers are double ordering into a softening environment, which is the setup for the sharpest inventory corrections. You need all five indicators running simultaneously, weighted by where we are in the cycle, to get a reliable read.
One more framing note: the indicators don't work uniformly across the industry. They're most actionable at the segment level, logic versus memory versus analog versus power semiconductors can be in completely different cycle positions simultaneously, and they have different structural sensitivities to each indicator. I'll call out the segment-specific behavior where it matters most.
Indicator One: Book-to-Bill (The Most Misread Number in Semiconductors)
I construct a proxy from quarterly transcript commentary at Avnet, Arrow, and the major IDMs and book to bills are currently sitting above 1.0. Order commentary at the major IDMs and fabless companies through Q1 2026 has been constructive across AI-adjacent segments, with mature-node bookings improving but not yet running hot. The bifurcation between AI allocation-driven demand and traditional cycle bookings is still the defining characteristic of the current order environment. No single public source today publishes a composite IC book-to-bill the way SIA did before 2017. However, TechInsights and others publish a paid monthly series that can be used as the closest current equivalent.
The mechanics: a ratio above 1.0 means orders are coming in faster than shipments are going out. Below 1.0, the reverse. Simple enough. The problem is the denominator. Billings are real revenue. Bookings are customer commitments, and customer commitments in semiconductors are notorious for being inflated during supply tightening. When lead times stretch past 26 weeks, as they did in 2021, customers book two to three times their actual demand to ensure allocation. They double-order, triple-order in extreme cases. The book-to-bill spikes and the street upgrades the sector. By the time customers start canceling orders (which they do quietly) in the back half of the cycle, billings are still strong because the backlog is being worked through, so the ratio compresses and looks "normalizing" right before the cliff.
The read I use: book-to-bill is most informative not as an absolute level but as a rate of change relative to lead time movement. When book-to-bill is still above 1.0 but lead times are already compressing, that's your sell signal. The order book is inflated, customers have more than enough on order, and the psychological shift from scarcity to adequacy is already underway. That's the transition that kills ASPs and utilization simultaneously, usually with a six-month lag to reported results.
On the other side of the cycle, book-to-bill tends to bottom after inventory days peak, sometimes significantly after. The ratio troughs when customers have burned through their on-hand inventory and are finally forced to place new orders. That sequence, inventory days rolling over followed by book-to-bill recovery, is your buy signal. Not the inventory days peak alone, but the confirmation handoff between the two.
Current context as of late Q1 2026: Book-to-bill has been running above 1 from aggregated commentary. Surface level constructive, but lead times in mature-node logic and microcontrollers have been flat to slightly compressing while bookings in AI-adjacent components (high-bandwidth memory, advanced packaging substrates, CoWoS capacity) remain severely backlogged. That bifurcation is a tale of two cycles running in parallel, which requires a segmented analysis rather than a composite view.
Indicator Two: Lead Times (The Tension Gauge)
Lead time data is harder to get cleanly than book-to-bill. The SIA doesn't publish it in a standardized form. You're pulling it from distributor surveys, supply chain consultancy trackers, and (most usefully) from the qualitative commentary in quarterly transcripts at companies like Avnet, Arrow, TTI, and direct customers in industrial and automotive. What you're building is a directional picture of how far out customers need to book to get product.
The lead time indicator tells you two things that no other single number captures: the current supply-demand tension in the market, and the credibility of the order book.
The 2020-2022 cycle was a masterclass in lead time distortion. Normal lead times for commodity microcontrollers run 8-16 weeks. At peak 2021, certain devices were quoted at 52+ weeks. The distortion wasn't all real demand. A significant portion was safety stock accumulation by OEMs and Tier 1 suppliers who had been burned by the automotive semiconductor shortage and were building buffer inventory as structural policy. That distinction matters enormously. Safety stock accumulation at elevated lead times looks identical to genuine end demand in the booking data. However, the moment lead times normalize to below the safety stock horizon, those orders evaporate.
The way I use lead times in the framework: I track them relative to their segment-specific historical average, not in absolute terms. A 20-week lead time for analog ICs is very different from a 20-week lead time for commodity DRAM. I'm looking at the standard deviation from the long-run mean for each category.
When lead times are more than 1.5 standard deviations above the historical mean, I assume the order book contains a meaningful inflation component and I discount book-to-bill accordingly. When lead times are compressing from elevated levels (even if they're still above average), I treat that as the signal that the inflation component is starting to unwind, and I start marking down estimates for the back half of the forward revenue window.
One segment-specific callout: power semiconductors and silicon carbide have had persistently above-average lead times even as broader semiconductor lead times normalized through 2023-2024. That structural tightness reflects real capacity constraints in substrate manufacturing, not demand inflation. When you're reading lead times across the sector, you need to be careful not to let the capacity-constrained niche segments contaminate the demand signal you're trying to read in the higher-volume commodity segments.
I spent nearly two decades watching lead times move in real time from inside the supply chain. The distinction between structural constraint and demand inflation is one that most models miss entirely because it only becomes visible when you're sitting inside the ecosystem, not observing it from outside.
Indicator Three: Inventory Days (The Cycle Clock)
If book-to-bill is the leading indicator and lead times are the tension gauge, inventory days at the customer level is the cycle clock. It tells you how much time is left in either the correction phase or the recovery phase with more precision than any other single metric.
I track three layers of inventory simultaneously: semiconductor company finished goods days on hand, distributor inventory weeks of supply, and OEM/customer inventory levels as reported in their own filings. The system matters because inventory corrections cascade from customer to distributor to chipmaker, and the timing of the cascade determines how long the down cycle lasts.
The typical correction sequence runs like this. OEM customers start building inventory during the up cycle because lead times force them to hold more safety stock. When demand softens, usually at the end product level first, before it shows up in the chip order data…OEMs have three to six months of excess inventory and stop ordering. Distributor sell-through falls, distributor inventory weeks of supply rise, distributors start canceling orders with chipmakers. The chipmaker sees booking cancellations, utilization starts to fall, and eventually reported inventory days at the fab level spike as units pile up in finished goods.
The key metric I watch most closely is distribution inventory weeks of supply, because distribution is the transmission mechanism that connects end-market demand signals to chipmaker production decisions. When distribution inventory normalizes to below 10 weeks (the historical lean-but-healthy level) that's when the recovery order flow starts. When it's above 14 weeks, chipmakers are still in the trough regardless of what the booking data says, because distributors won't reorder until they've worked down their own position.
Some nuance here, the 10-week threshold is a useful rule of thumb but the current cycle has fractured it. Analog and industrial distribution normalized through Q1 2026, memory distribution is structurally depleted, and AI silicon doesn't trade through distribution at all, so it is important to track these three channels separately. The current AI memory environment has a unique distortion worth flagging: consumer DRAM is not bloated, it's actually tight and getting tighter. The HBM capacity reallocation is a zero-sum game. Every wafer Samsung, SK Hynix, and Micron allocate to HBM for AI infrastructure is a wafer pulled from conventional DRAM production. Consumer and PC DRAM inventory at OEMs is at critically low levels, with PC DRAM prices having surged dramatically in early 2026. The divergence to watch is HBM shortage driving a secondary consumer DRAM shortage, with completely different pricing dynamics in each segment."
Threshold: The classic thresholds of fabless above 150 days warning, below 100 days entry, need a 2026 asterisk. Apply them to analog and industrial fabless names where the traditional cycle still governs. Do not apply them to AI-exposed fabless companies where strategic inventory hoarding by hyperscalers has permanently distorted the signal. For memory, distributor inventory days are essentially irrelevant. The constraint is wafer allocation, not channel inventory. Takeaway here is segmenting you inventory analysis.
Indicator Four: Utilization Rates
Fab utilization is the most honest number in semiconductors because you cannot fake it for long. A fab running at 70% utilization is burning cash on fixed costs with no revenue to show for it. Management will cut capex, defer expansions, and eventually idle equipment, all of which show up 12 to 18 months later as supply constraints when demand recovers.
What I watch: TSMC's utilization commentary on earnings calls is the single most important data point in the entire semiconductor ecosystem every quarter. When they describe leading-edge utilization separately from mature node utilization, they are telling you exactly where the cycle is bifurcating. Leading-edge tight, mature loose = AI-driven demand with everything else still working through excess. Both tight = broad-based recovery. Both loose = full cycle downturn.
The secondary signal I track is equipment vendor commentary on tool utilization at customer sites. ASML, Applied Materials, and Lam Research all give you indirect utilization reads through their service revenue lines. When service revenue grows faster than equipment revenue, customers are sweating their existing tools harder rather than buying new ones. That's a late-cycle signal worth noting.
Threshold: In a pre AI world these are good rule of thumbs. Industry-wide utilization below 80% = oversupply conditions, watch for pricing pressure. Above 90% sustained = supply tightness incoming, lead times will extend within 2 quarters. The 80%/90% industry-wide thresholds are artifacts of a pre-AI cycle when utilization by node moved together. In 2026 that metric has bifurcated permanently. Track them separately: leading-edge (sub-5nm) utilization is effectively at ceiling and has been for 18 months. The actionable utilization read is now mature nodes…8-inch running at ~75% and 12-inch mature at ~76% means there is still meaningful slack in the nodes that serve automotive, industrial, and analog. Watch for those numbers crossing 85%+ sustained. That is your signal that the broad-based recovery has arrived and the entire supply chain is tightening, not just AI.
Indicator Five: Average Selling Prices (ASPs)
ASPs are a lagging indicator but they confirm what the other four are telling you, and when they diverge from what the cycle signals suggest, that divergence is itself the signal.
What I watch: the spread between contract ASPs and spot ASPs is more informative than either number in isolation. When spot prices trade at a premium to contract, customers are paying up to secure supply outside their normal agreements. Demand is outrunning the contracted supply chain. When spot trades at a discount, customers are offloading excess inventory into the open market. That spread tells you where real supply-demand balance sits before it shows up in any reported earnings number.
For memory specifically, I track DRAM and NAND spot prices weekly. The speed of ASP movement matters as much as direction. A 5% monthly decline is manageable and may reflect normal mix shift. A 15% monthly decline means someone large is dumping inventory and the cycle is deteriorating faster than consensus models.
The current environment has a unique distortion worth flagging: AI chip ASPs are structurally elevated and somewhat decoupled from the traditional cycle because demand is driven by hyperscaler capex budgets rather than consumer end markets. Do not blend AI chip ASPs with commodity logic or memory ASPs as they are pricing off completely different supply-demand curves.
Threshold: Spot-to-contract premium above 10% sustained for 2+ months = supply tightening, cycle inflecting up. Spot-to-contract discount widening month-over-month = inventory liquidation in progress, cycle deteriorating.
The Framework in Practice
These five indicators rarely all point in the same direction simultaneously, and that's exactly the point. The cycle edge comes from reading the composite signal when they start to converge.
The setup I've seen precede every major upcycle in my 20+ years: book-to-bill crossing above 1.1, lead times extending from 2 or more vendors simultaneously, inventory days falling below 100 at fabless companies, utilization climbing past 85% at leading-edge fabs, and spot ASPs moving to premium versus contract. When four of five are aligned, you don't wait for the fifth.
We're not there yet across the board in 2026. But two of these indicators are already flashing early-cycle green. I'll be tracking all five in every issue going forward, consider this your baseline.
Next issue: TSMC's $52–56B capex commitment and what the spending mix tells us about foundry economics for the next 18 months.